On Mon, Mar 29, 2021 at 01:41:28PM +0800, Like Xu wrote:
> +     if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) {
> +             if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) {
> +                     pmu->pebs_enable_mask = ~pmu->global_ctrl;
> +                     pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE;
> +                     for (i = 0; i < pmu->nr_arch_fixed_counters; i++)
> +                             pmu->fixed_ctr_ctrl_mask &=
> +                                     ~(1ULL << (INTEL_PMC_IDX_FIXED + i * 
> 4));

{ }

> +             } else
> +                     pmu->pebs_enable_mask = ~((1ull << 
> pmu->nr_arch_gp_counters) - 1);

{ }

> +     } else {
> +             vcpu->arch.perf_capabilities &= ~PERF_CAP_PEBS_MASK;

as you already do here..

> +     }
>  }

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