On 12/04/21 10:37, Mel Gorman wrote: > On Mon, Apr 12, 2021 at 11:54:36AM +0530, Srikar Dronamraju wrote: >> * Gautham R. Shenoy <e...@linux.vnet.ibm.com> [2021-04-02 11:07:54]: >> >> > >> > To remedy this, this patch proposes that the LLC be moved to the MC >> > level which is a group of cores in one half of the chip. >> > >> > SMT (SMT4) --> MC (Hemisphere)[LLC] --> DIE >> > >> >> I think marking Hemisphere as a LLC in a P10 scenario is a good idea. >> >> > While there is no cache being shared at this level, this is still the >> > level where some amount of cache-snooping takes place and it is >> > relatively faster to access the data from the caches of the cores >> > within this domain. With this change, we no longer see regressions on >> > P10 for applications which require single threaded performance. >> >> Peter, Valentin, Vincent, Mel, etal >> >> On architectures where we have multiple levels of cache access latencies >> within a DIE, (For example: one within the current LLC or SMT core and the >> other at MC or Hemisphere, and finally across hemispheres), do you have any >> suggestions on how we could handle the same in the core scheduler? >> > > Minimally I think it would be worth detecting when there are multiple > LLCs per node and detecting that in generic code as a static branch. In > select_idle_cpu, consider taking two passes -- first on the LLC domain > and if no idle CPU is found then taking a second pass if the search depth > allows within the node with the LLC CPUs masked out.
I think that's actually a decent approach. Tying SD_SHARE_PKG_RESOURCES to something other than pure cache topology in a generic manner is tough (as it relies on murky, ill-defined hardware fabric properties). Last I tried thinking about that, I stopped at having a core-to-core latency matrix, building domains off of that, and having some knob specifying the highest distance value below which we'd set SD_SHARE_PKG_RESOURCES. There's a few things I 'hate' about that; for one it makes cpus_share_cache() somewhat questionable. > While there would be > a latency hit because cache is not shared, it would still be a CPU local > to memory that is idle. That would potentially be beneficial on Zen* > as well without having to introduce new domains in the topology hierarchy. > > -- > Mel Gorman > SUSE Labs
