On 25/1/08 22:54, "Jeremy Fitzhardinge" <[EMAIL PROTECTED]> wrote:
> The only possibly relevant comment I can find in vol3a is: > > Older IA-32 processors that implement the PAE mechanism use uncached > accesses when loading page-directory-pointer table entries. This > behavior is > model specific and not architectural. More recent IA-32 processors may > cache page-directory-pointer table entries. Go read the Intel application note "TLBs, Paging-Structure Caches, and Their Invalidation" at http://www.intel.com/design/processor/applnots/317080.pdf Section 8.1 explains about the PDPTR cache in 32-bit PAE mode, which can only be refreshed by appropriate tickling of CR0, CR3 or CR4. It is also important to note that *any* valid page directory entry at *any* level in the page-table hierarchy can become cached at *any* time. Basically TLB lookup is performed as a longest-prefix match on the linear address to skip as many levels in a page-table walk as possible (where a walk is needed, because there is no full-length match on the linear address). So, if you modify a directory entry from present to not-present, or change the page directory that a valid pde points to, you probably need to flush the pde caching structure. One piece of good news is that all pde caches are flushed by any arbitrary INVLPG. -- Keir -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
