On 29.09.2023 09:31, Luca Weiss wrote: > Add the USB3+DP Combo QMP PHY port subnodes in the SC7280 SoC DTSI to > avoid duplication in the devices DTs. The rationale here is to make describing the connections between certain hw blocks possible. Defining it in the soc dtsi gives us a very cool side-effect of not having to repeat this, but it's not the main point here
With the commit msg amended: Reviewed-by: Konrad Dybcio <konrad.dyb...@linaro.org> Konrad
