Add the USB3+DP Combo QMP PHY port subnodes to facilitate the description of the connection between the hardware blocks.
Put it in the SoC DTSI to avoid duplication in the device DTs. Reviewed-by: Konrad Dybcio <konrad.dyb...@linaro.org> Signed-off-by: Luca Weiss <luca.we...@fairphone.com> --- Changes in v2: - Update commit message after feedback from Konrad - Pick up tags - Link to v1: https://lore.kernel.org/r/20230929-sc7280-qmpphy-ports-v1-1-7532c1197...@fairphone.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 66f1eb83cca7..4e34d00e246b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3399,6 +3399,32 @@ usb_1_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_2: usb@8cf8800 { --- base-commit: df964ce9ef9fea10cf131bf6bad8658fde7956f6 change-id: 20230929-sc7280-qmpphy-ports-20afd4212470 Best regards, -- Luca Weiss <luca.we...@fairphone.com>
