Add the node for the ADSP found on the SC7280 SoC, using standard
Qualcomm firmware.
Signed-off-by: Luca Weiss <luca.we...@fairphone.com>
---
arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 5 --
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 --
arch/arm64/boot/dts/qcom/sc7280.dtsi | 74 ++++++++++++++++++++++
3 files changed, 74 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
index cb78b03bd831..92be951fc0e4 100644
--- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
+++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts
@@ -75,11 +75,6 @@ cont_splash_mem: cont-splash@e1000000 {
no-map;
};
- adsp_mem: adsp@86700000 {
- reg = <0x0 0x86700000 0x0 0x2800000>;
- no-map;
- };
-
cdsp_mem: cdsp@88f00000 {
reg = <0x0 0x88f00000 0x0 0x1e00000>;
no-map;
diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
index 14511a69658c..9cbe0fe64420 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
@@ -24,11 +24,6 @@
/ {
reserved-memory {
- adsp_mem: memory@86700000 {
- reg = <0x0 0x86700000 0x0 0x2800000>;
- no-map;
- };
-
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8c21695646c6..2b11ccc9a6b8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -142,6 +142,11 @@ wlan_fw_mem: wlan-fw@80c00000 {
no-map;
};
+ adsp_mem: adsp@86700000 {
+ reg = <0x0 0x86700000 0x0 0x2800000>;
+ no-map;
+ };
+
video_mem: video@8b200000 {
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
@@ -3588,6 +3593,75 @@ qspi: spi@88dc000 {
status = "disabled";
};
+ remoteproc_adsp: remoteproc@3700000 {
+ compatible = "qcom,sc7280-adsp-pas";
+ reg = <0 0x03700000 0 0x100>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&adsp_smp2p_in 0
IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1
IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2
IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3
IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 7
IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal", "ready", "handover",
+ "stop-ack", "shutdown-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd SC7280_LCX>,
+ <&rpmhpd SC7280_LMX>;
+ power-domain-names = "lcx", "lmx";
+
+ memory-region = <&adsp_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+
IPCC_MPROC_SIGNAL_GLINK_QMP
+
IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels =
"fastrpcglink-apps-dsp";
+ label = "adsp";
+ qcom,non-secure-domain;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@3 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x1803
0x0>;
+ };
+
+ compute-cb@4 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x1804
0x0>;
+ };
+
+ compute-cb@5 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x1805
0x0>;
+ };
+ };
+ };
+ };
+
remoteproc_wpss: remoteproc@8a00000 {
compatible = "qcom,sc7280-wpss-pas";
reg = <0 0x08a00000 0 0x10000>;
--
2.42.1
