On Fri, 25 Apr 2025 14:12:54 +0200, Luca Weiss wrote:
> As described in the commit messages, keep the GDSC configs aligned with
> the downstream kernel.
>
> For reference, this was checked using the following code:
>
> To: Bjorn Andersson <[email protected]>
> To: Michael Turquette <[email protected]>
> To: Stephen Boyd <[email protected]>
> To: Konrad Dybcio <[email protected]>
> To: AngeloGioacchino Del Regno <[email protected]>
> Cc: ~postmarketos/[email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
>
> [...]
Applied, thanks!
[0/4] Add *_wait_val values for GDSCs in all SM6350 clock drivers
(no commit info)
[1/4] clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs
commit: e7b1c13280ad866f3b935f6c658713c41db61635
[2/4] clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs
commit: 673989d27123618afab56df1143a75454178b4ae
[3/4] clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
commit: afdfd829a99e467869e3ca1955fb6c6e337c340a
[4/4] clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs
commit: d988b0b866c2aeb23aa74022b5bbd463165a7a33
Best regards,
--
Bjorn Andersson <[email protected]>
