Hi Sergey, On Sun, Dec 14, 2025 at 10:35 AM Sergey Matyukevich <[email protected]> wrote: > > Add strict validation for vector csr registers when setting them via > ptrace: > - reject attempts to set reserved bits or invalid field combinations > - enforce strict VL checks against calculated VLMAX values > > Vector specs 0.7.1 and 1.0 allow normal applications to set candidate > VL values and read back the hardware-adjusted results, see section 6 > for details. Disallow such flexibility in vector ptrace operations > and strictly enforce valid VL input. > > The traced process may not update its saved vector context if no vector > instructions execute between breakpoints. So the purpose of the strict > ptrace approach is to make sure that debuggers maintain an accurate view > of the tracee's vector context across multiple halt/resume debug cycles. > > Signed-off-by: Sergey Matyukevich <[email protected]>
Reviewed-by: Andy Chiu <[email protected]> Thanks, Andy
