On Wed, Jan 21, 2026, Jim Mattson wrote: > If the vCPU advertises SVM and uses the mediated PMU, allow the guest to > set the Host-Only and Guest-Only bits in the event selector MSRs. > > Signed-off-by: Jim Mattson <[email protected]> > --- > arch/x86/kvm/svm/pmu.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c > index 85155d65fa38..a1eeb7b38219 100644 > --- a/arch/x86/kvm/svm/pmu.c > +++ b/arch/x86/kvm/svm/pmu.c > @@ -262,8 +262,13 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) > pmu->global_status_rsvd = pmu->global_ctrl_rsvd; > } > > - pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1; > pmu->reserved_bits = 0xfffffff000280000ull; > + if (guest_cpu_cap_has(vcpu, X86_FEATURE_SVM) && > + kvm_vcpu_has_mediated_pmu(vcpu)) > + /* Allow Host-Only and Guest-Only bits */
Meh, no comment needed if the macro is more descriptive. > + pmu->reserved_bits &= ~AMD64_EVENTSEL_HG_ONLY; > + > + pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1; Spurious code movement? > pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; > /* not applicable to AMD; but clean them to prevent any fall out */ > pmu->counter_bitmask[KVM_PMC_FIXED] = 0; > -- > 2.52.0.457.g6b5491de43-goog >
