To make sure the display subsystem starts in a predictable state, we
need to reset it. On closely related SoC (sm6115) this has caused
DSI displays to not work.

Wire up the reset to fix.

Fixes: 0865d23a0226 ("arm64: dts: qcom: sm6125: Add display hardware nodes")
Signed-off-by: Val Packett <[email protected]>
---
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi 
b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 80c42dff5399..a22374e5a17f 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -1238,6 +1238,8 @@ mdss: display-subsystem@5e00000 {
                                      "ahb",
                                      "core";
 
+                       resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
                        power-domains = <&dispcc MDSS_GDSC>;
 
                        iommus = <&apps_smmu 0x400 0x0>;
@@ -1437,6 +1439,7 @@ dispcc: clock-controller@5f00000 {
                        power-domains = <&rpmpd RPMPD_VDDCX>;
 
                        #clock-cells = <1>;
+                       #reset-cells = <1>;
                        #power-domain-cells = <1>;
                };
 
-- 
2.52.0


Reply via email to