On 28/04/2026 11:04, Michal Simek wrote: > > > On 4/28/26 10:47, Krzysztof Kozlowski wrote: >> On 28/04/2026 10:33, Michal Simek wrote: >>> >>> >>> On 4/28/26 08:50, Krzysztof Kozlowski wrote: >>>> On Mon, Apr 27, 2026 at 09:27:02AM -0700, Ben Levinsky wrote: >>>>> Describe an AMD BRAM-based soft-core processor subsystem instantiated in >>>>> programmable logic and using dual-port BRAM for firmware storage and >>>>> execution. >>>>> >>>>> The binding models a soft-core processor subsystem instantiated in AMD >>>>> programmable logic and using dual-port BRAM for firmware storage and >>>>> execution. The remoteproc device is represented as a child node whose >>>>> reg property describes the firmware memory window in the processor-local >>>>> address space. The parent bus node provides standard devicetree address >>>>> translation through ranges so Linux can access the same BRAM through the >>>>> system physical address space. >>>>> >>>>> A clock input feeds the soft-core processor subsystem, and an active-low >>>>> reset GPIO holds the processor in reset until firmware loading >>>>> completes. The firmware-name property is optional. >>>>> >>>>> Signed-off-by: Ben Levinsky <[email protected]> >>>>> --- >>>>> .../bindings/remoteproc/amd,bram-rproc.yaml | 98 +++++++++++++++++++ >>>>> 1 file changed, 98 insertions(+) >>>>> create mode 100644 >>>>> Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml >>>>> >>>>> diff --git >>>>> a/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml >>>>> b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..f16657dc0d9f >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml >>>>> @@ -0,0 +1,98 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/remoteproc/amd,bram-rproc.yaml# >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: AMD BRAM-based Remote Processor >>>>> + >>>>> +maintainers: >>>>> + - Ben Levinsky <[email protected]> >>>>> + >>>>> +description: | >>>>> + Soft-core processor subsystem instantiated in AMD programmable logic >>>>> and >>>>> + using dual-port BRAM for firmware storage and execution. >>>> >>>> Isn't the soft-core or FPGA still part of some Xilinx SoC? Or is this >>>> completely different thing from SoC and there is a design WITHOUT SoC >>>> using this remote proc? >>> >>> In 99% case this is going to be used on Xilinx SOC with programmable logic >>> next >>> to ARM core. >>> soft core means - means VHDL/Verilog code synthesized to programmable >>> logic/fpga. It means exact location in chip varies based on build and >>> constraints. >>> >>> hard core - physical HW location - like ARM cores in our chip. >>> >>> (ARM is providing RTL/code that even ARM cores in fpga emulated platforms >>> are >>> actually used as soft cores). >>> >>> Not sure if you want me to talk about that 1% use cases which are also >>> possible >>> but don't think anybody will design them. >> >> Then I would treat it exactly like every other block of a SoC - you need >> a SoC specific compatible. If there is a fallback, SoC specific >> compatible should be used in the fallback as well - that's all already >> documented in writing-bindings. > > But which SOC? We have ZynqMP, Versal, Versal NET, Versal Gen 2. And all of > these will use this configuration. > Do you want to list all of them?
"Then I would treat it exactly like every other block of a SoC" Best regards, Krzysztof
