On Thu, 07 May 2026 22:36:21 -0700, Changhuang Liang wrote: > Add bindings for the Peripheral-0 clock and reset generator (PER0CRG) > on the JHB100 RISC-V SoC by StarFive Ltd. > > Signed-off-by: Changhuang Liang <[email protected]> > --- > .../clock/starfive,jhb100-per0crg.yaml | 70 +++++ > .../dt-bindings/clock/starfive,jhb100-crg.h | 281 ++++++++++++++++++ > .../dt-bindings/reset/starfive,jhb100-crg.h | 77 +++++ > 3 files changed, 428 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml >
Reviewed-by: Rob Herring (Arm) <[email protected]>
