On 21/05/2026 11:42, Kevin Brodsky wrote: > It isn't completely obvious why user page types do not have overlays > applied in PIE_EL1. Add a comment to that effect, to avoid > unpleasant surprises in the future.
Should probably s/PIE_EL1/PIR_EL1/ in this whole patch. I'm also tempted to rename PIE_E* to PIR_E* to avoid anyone else's brain being confused like mine... The extension is called PIE, but this is really about the register configuration, i.e. PIR. - Kevin > Signed-off-by: Kevin Brodsky <[email protected]> > --- > arch/arm64/include/asm/pgtable-prot.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/include/asm/pgtable-prot.h > b/arch/arm64/include/asm/pgtable-prot.h > index 212ce1b02e15..6e2f99820909 100644 > --- a/arch/arm64/include/asm/pgtable-prot.h > +++ b/arch/arm64/include/asm/pgtable-prot.h > @@ -175,6 +175,13 @@ static inline bool __pure lpa2_is_enabled(void) > PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_READONLY), PIE_R_O) | \ > PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_SHARED), PIE_RW_O)) > > +/* > + * Regular user page types such as _PAGE_SHARED must not have overlays > applied > + * in PIE_EL1. If POE is enabled at EL1, and in the absence of FEAT_LSUI, > this > + * would break futex atomic operations on user memory with a non-default > + * POIndex; the privileged atomic load/store instructions would be mistakenly > + * checked against POR_EL1. > + */ > #define PIE_E1 ( \ > PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS), PIE_NONE_O) | \ > PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS_RO), PIE_NONE_O) | \ >
