On Wed, Jun 03, 2026 at 07:12:03AM -0400, Guodong Xu wrote:
> Zic64b mandates 64-byte naturally aligned cache blocks and is a
> mandatory extension of the RVA22 and RVA23 profiles. Allocate a
> RISCV_ISA_EXT_ZIC64B id, parse "zic64b" from the ISA string with a
> validate callback that requires cbom/cbop/cboz cache block sizes of 64
> bytes, and export it through hwprobe.
>
> Signed-off-by: Guodong Xu <[email protected]>
> ---
> v3: New patch.
> ---
> Documentation/arch/riscv/hwprobe.rst | 3 +++
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/include/uapi/asm/hwprobe.h | 1 +
> arch/riscv/kernel/cpufeature.c | 18 ++++++++++++++++++
> arch/riscv/kernel/sys_hwprobe.c | 1 +
> 5 files changed, 24 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst
> b/Documentation/arch/riscv/hwprobe.rst
> index 002d5046ab689..601e81f561421 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -425,3 +425,6 @@ The following keys are defined:
> * :c:macro:`RISCV_HWPROBE_EXT_B`: The B extension is supported, as defined
> in version 1.0 of the Bit-Manipulation ISA extensions, and implies the
> presence of the Zba, Zbb, and Zbs sub-extensions.
Need a blank line here.
> + * :c:macro:`RISCV_HWPROBE_EXT_ZIC64B`: The Zic64b extension is supported,
> + as defined in the RISC-V Profiles specification starting from commit
> + b1d80660 ("Updated to ratified state.")
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 58523b3a1998a..36572c1ff438a 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -117,6 +117,7 @@
> #define RISCV_ISA_EXT_ZICCAMOA 107
> #define RISCV_ISA_EXT_ZICCIF 108
> #define RISCV_ISA_EXT_ZA64RS 109
> +#define RISCV_ISA_EXT_ZIC64B 110
>
> #define RISCV_ISA_EXT_XLINUXENVCFG 127
>
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h
> b/arch/riscv/include/uapi/asm/hwprobe.h
> index 430dc49a82863..36ec8ab470423 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -122,6 +122,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZICCRSE (1ULL << 4)
> #define RISCV_HWPROBE_EXT_ZA64RS (1ULL << 5)
> #define RISCV_HWPROBE_EXT_B (1ULL << 6)
> +#define RISCV_HWPROBE_EXT_ZIC64B (1ULL << 7)
>
> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index e0197160af6dd..79ff431768139 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -154,6 +154,23 @@ static int riscv_ext_zicbop_validate(const struct
> riscv_isa_ext_data *data,
> return 0;
> }
>
> +static int riscv_ext_zic64b_validate(const struct riscv_isa_ext_data *data,
> + const unsigned long *isa_bitmap)
> +{
> + /*
> + * Zic64b mandates 64-byte naturally aligned cache blocks; cross-check
> the
> + * cbom/cbop/cboz block-size device-tree properties to avoid
> inconsistency.
> + */
> + if (riscv_cbom_block_size != 64 ||
> + riscv_cbop_block_size != 64 ||
> + riscv_cboz_block_size != 64) {
> + pr_err("Zic64b detected in ISA string, disabling as the cache
> block size is not 64 bytes\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data,
> const unsigned long *isa_bitmap)
> {
> @@ -524,6 +541,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),
> __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_V, riscv_v_exts,
> riscv_ext_vector_float_validate),
> __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_H),
> + __RISCV_ISA_EXT_DATA_VALIDATE(zic64b, RISCV_ISA_EXT_ZIC64B,
> riscv_ext_zic64b_validate),
> __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM,
> riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
> __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP,
> riscv_ext_zicbop_validate),
> __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ,
> riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index dcc102bf8f183..3e80e5551ae0d 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -211,6 +211,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
> EXT_KEY(isainfo->isa, ZICCRSE, pair->value, missing);
> EXT_KEY(isainfo->isa, ZA64RS, pair->value, missing);
> EXT_KEY(isainfo->isa, B, pair->value, missing);
> + EXT_KEY(isainfo->isa, ZIC64B, pair->value, missing);
> }
>
> /* Now turn off reporting features if any CPU is missing it. */
>
> --
> 2.43.0
>
Other than the missing blank line,
Reviewed-by: Andrew Jones <[email protected]>
