[PATCH 06/21] perf: arm_pmuv3: Allocate counter indices from high to low

[Colton Lewis]

To minimize collisions between host and guest counters, allocate host
counters from high to low. How the pivot HPMN is defined to partition the 
counters gives the guest the low index counters.

Doing this with index math instead of defining a
for_each_set_bit_reverse macro is safe because cntr_mask is always a
dense range while the host is running.

Signed-off-by: Colton Lewis <coltonle...@google.com>
---
 drivers/perf/arm_pmuv3.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c
index 17bb1cfdc271c..d7a49dc0b0be6 100644
--- a/drivers/perf/arm_pmuv3.c
+++ b/drivers/perf/arm_pmuv3.c
@@ -953,10 +953,12 @@ static int armv8pmu_get_single_idx(struct pmu_hw_events 
*cpuc,
 {
        int idx;
 
-       for_each_set_bit(idx, cpu_pmu->cntr_mask, 
ARMV8_PMU_MAX_GENERAL_COUNTERS) {
-               if (!test_and_set_bit(idx, cpuc->used_mask))
+       for (idx = ARMV8_PMU_MAX_GENERAL_COUNTERS - 1; idx >= 0; idx--) {
+               if (test_bit(idx, cpu_pmu->cntr_mask) &&
+                   !test_and_set_bit(idx, cpuc->used_mask))
                        return idx;
        }
+
        return -EAGAIN;
 }
 
@@ -969,17 +971,22 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events 
*cpuc,
         * Chaining requires two consecutive event counters, where
         * the lower idx must be even.
         */
-       for_each_set_bit(idx, cpu_pmu->cntr_mask, 
ARMV8_PMU_MAX_GENERAL_COUNTERS) {
+       for (idx = ARMV8_PMU_MAX_GENERAL_COUNTERS - 1; idx >= 0; idx--) {
                if (!(idx & 0x1))
                        continue;
-               if (!test_and_set_bit(idx, cpuc->used_mask)) {
-                       /* Check if the preceding even counter is available */
-                       if (!test_and_set_bit(idx - 1, cpuc->used_mask))
-                               return idx;
-                       /* Release the Odd counter */
-                       clear_bit(idx, cpuc->used_mask);
+
+               if (test_bit(idx, cpu_pmu->cntr_mask) &&
+                   test_bit(idx - 1, cpu_pmu->cntr_mask)) {
+                       if (!test_and_set_bit(idx, cpuc->used_mask)) {
+                               /* Check if the preceding even counter is 
available */
+                               if (!test_and_set_bit(idx - 1, cpuc->used_mask))
+                                       return idx;
+                               /* Release the Odd counter */
+                               clear_bit(idx, cpuc->used_mask);
+                       }
                }
        }
+
        return -EAGAIN;
 }
 
-- 
2.54.0.1136.gdb2ca164c4-goog