On Wed, Jul 29, 2026 at 10:19:58PM +0200, David Heidelberg wrote: > So far, only D-PHY mode was supported, which uses even bits when enabling > or masking lanes. For C-PHY configuration, the hardware instead requires > using the odd bits. > > Since there can be unrecognized configuration allow returning failure. > > Acked-by: Cory Keitz <[email protected]> > Reviewed-by: Bryan O'Donoghue <[email protected]> > Signed-off-by: David Heidelberg <[email protected]> > ---
Reviewed-by: Frank Li <[email protected]> > .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 25 > ++++++++++++++-------- > 1 file changed, 16 insertions(+), 9 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 7c8c0e41bc62f..dfcd9ed2eb7a3 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -9,16 +9,17 @@ > */ > > #include "camss.h" > #include "camss-csiphy.h" > > #include <linux/delay.h> > #include <linux/interrupt.h> > #include <linux/io.h> > +#include <linux/media-bus-format.h> > > #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) > #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) > #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) > #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 > @@ -1108,23 +1109,32 @@ static void csiphy_gen2_config_lanes(struct > csiphy_device *csiphy, > writel_relaxed(val, csiphy->base + r->reg_addr); > if (r->delay_us) > udelay(r->delay_us); > } > } > > static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) > { > - u8 lane_mask; > - int i; > + u8 lane_mask = 0; > + u8 offset = 0; > > - lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > + switch (lane_cfg->phy_cfg) { > + case V4L2_MBUS_CSI2_CPHY: > + offset = 1; > + break; > + case V4L2_MBUS_CSI2_DPHY: > + lane_mask = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > + break; > + default: > + break; > + } > > - for (i = 0; i < lane_cfg->num_data; i++) > - lane_mask |= BIT(lane_cfg->data[i].pos * 2); > + for (int i = 0; i < lane_cfg->num_data; i++) > + lane_mask |= BIT((lane_cfg->data[i].pos * 2) + offset); > > return lane_mask; > } > > static bool csiphy_is_gen2(u32 version) > { > bool ret = false; > > @@ -1155,20 +1165,17 @@ static void csiphy_lanes_enable(struct csiphy_device > *csiphy, > struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; > struct csiphy_device_regs *regs = csiphy->regs; > u8 settle_cnt; > u8 val; > int i; > > settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); > > - val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; > - for (i = 0; i < c->num_data; i++) > - val |= BIT(c->data[i].pos * 2); > - > + val = csiphy_get_lane_mask(c); > writel_relaxed(val, csiphy->base + > CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); > > val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; > writel_relaxed(val, csiphy->base + > CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); > > val = 0x02; > > -- > 2.53.0 >
