On Tue, Aug 04, 2026 at 02:06:20PM -0400, Esteban Urrutia via B4 Relay wrote: > From: Esteban Urrutia <[email protected]> > > Has been tested with the following capabilities: > - USB Type-C at 10Gb/s > - DP Alt Mode, using HBR2 > - USB Type-C at 480Mb/s + DP Alt Mode, using HBR2 > > RX and PCS USB tables had to be added, while serdes, TX and PCS tables were > reused from other SoCs. > > Some SoCs such as SAR2130P, SM7550, SM7635 and SM8475 use 4nm-v1 PLLs. > For SM8475, trying to use qmp_v6_dp_serdes_tbl structs (which are for > 4nm-v1.1 PLLs) causes link training to fail because of ref clock > differences, which in turn makes these structs differ. > Add structs for v1 PLLs as well. > > Signed-off-by: Esteban Urrutia <[email protected]> > --- > drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 169 > ++++++++++++++++++++++++++++++ > 1 file changed, 169 insertions(+) >
Reviewed-by: Dmitry Baryshkov <[email protected]> -- With best wishes Dmitry
