Hi there, This patchset introduces clock driver support for the Exynos5515 SoC.
Currently, the following CMU blocks are defined: - CMU_TOP (handles clocks for all child CMU blocks) - CMU_PERI (handles clocks for USI, watchdog timer, etc) - CMU_FSYS (handles clocks for MMC, USB, etc) This driver support makes use of HWACG (hardware automatic clock gating), so gates do not need to be manually forced on with CLK_IGNORE_UNUSED or CLK_IS_CRITICAL. Rather, the hardware handles the clock gating. Support for more blocks to come as support for the the hardware requiring them is added. I am getting some checkpatch warnings telling me to check the MAINTAINERS file, as new files have been added. I am assuming these can be ignored as I am not a maintainer, and the whole clock driver and samsung subsystems already have maintainers listed. Kind regards, - Aiden Isik Signed-off-by: Aiden Isik <[email protected]> --- Aiden Isik (3): dt-bindings: clock: Add Exynos5515 SoC clk: samsung: clk-pll: Add support for pll_309 clk: samsung: Introduce Exynos5515 clock driver .../bindings/clock/samsung,exynos5515-cmu.yaml | 145 ++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5515.c | 1485 ++++++++++++++++++++ drivers/clk/samsung/clk-pll.c | 57 +- drivers/clk/samsung/clk-pll.h | 1 + include/dt-bindings/clock/samsung,exynos5515-cmu.h | 191 +++ 6 files changed, 1854 insertions(+), 26 deletions(-) --- base-commit: acde40ba506aae78633e080b5704d33cf4bc13c6 change-id: 20260815-for-next-lucky7-clock-3b4b7e6b1ce4 Best regards, -- Aiden Isik <[email protected]>
