On Wed, Aug 19, 2026 at 02:41:13PM +0100, Leonardo Bras wrote: > On Wed, Aug 12, 2026 at 08:12:00PM +0100, Mark Brown wrote:
> > + /* Disable traps of GCS instructions at EL1 */ > > + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK > > + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK > > + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK > Which I understand to be the way of us saying that EL2 will not interfere > on nor manage those instructions that let software change the entries of > GCS. Is that correct? Yes, the goal is to allow EL1 to manage things how it wants (there are controls for store and push in GCSCR_EL1 too). > As for the asm routine, x2 at this point have nBRBIALL and nBRBINJ already > set, and will be loaded to SYS_HFGITR_EL2 in the next block of > instructions. > Did I get it right? Is there any missing detail here? That's the idea.
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