Hi Changhuang, > Add support for JHB100 System-2 clock generator (SYS2CRG). > > Signed-off-by: Changhuang Liang <[email protected]> > > diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig > index 11da8bcc4046..cfaac934a8e0 100644 > --- a/drivers/clk/starfive/Kconfig > +++ b/drivers/clk/starfive/Kconfig > @@ -92,3 +92,13 @@ config CLK_STARFIVE_JHB100_SYS1 > help > Say yes here to support the system-1 clock controller on the > StarFive JHB100 SoC. > + > +config CLK_STARFIVE_JHB100_SYS2 > + bool "StarFive JHB100 system-2 clock support" > + depends on ARCH_STARFIVE || COMPILE_TEST > + select CLK_STARFIVE_JH71X0 > + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER > + default ARCH_STARFIVE > + help > + Say yes here to support the system-2 clock controller on the > + StarFive JHB100 SoC. > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile > index 0061550e0f7e..29cdef20575e 100644 > --- a/drivers/clk/starfive/Makefile > +++ b/drivers/clk/starfive/Makefile > @@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += > clk-starfive-jh7110-vout.o > > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += > clk-starfive-jhb100-sys0.o > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += > clk-starfive-jhb100-sys1.o > +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += > clk-starfive-jhb100-sys2.o > diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys2.c > b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c > new file mode 100644 > index 000000000000..a2c7e8eba9b6 > --- /dev/null > +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c > @@ -0,0 +1,129 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * StarFive JHB100 System-2 Clock Driver > + * > + * Copyright (C) 2024 StarFive Technology Co., Ltd. > + * > + * Author: Changhuang Liang <[email protected]> > + * > + */ > + > +#include <dt-bindings/clock/starfive,jhb100-crg.h> > +#include <linux/init.h> > +#include <linux/platform_device.h> > + > +#include "clk-starfive-jh71x0.h" > + > +#define JHB100_SYS2CLK_NUM_CLKS > (JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 + 1) > + > +/* external clocks */ > +#define JHB100_SYS2CLK_OSC (JHB100_SYS2CLK_NUM_CLKS + 0) > +#define JHB100_SYS2CLK_PLL1 (JHB100_SYS2CLK_NUM_CLKS + 1) > +#define JHB100_SYS2CLK_GPU0_NCNOC_INIT > (JHB100_SYS2CLK_NUM_CLKS + 2) > +#define JHB100_SYS2CLK_GPU1_NCNOC_INIT > (JHB100_SYS2CLK_NUM_CLKS + 3) > + > +static const char * const jhb100_sys2_ext_clk[] = { > + "osc", > + "pll1", > + "gpu0_ncnoc_init", > + "gpu1_ncnoc_init", > +}; > + > +static const struct jh71x0_clk_data jhb100_sys2crg_clk_data[] = { > + /* jtag mst*/ > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_HCLK, "jtagm0_hclk", 6, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_HCLK, "jtagm1_hclk", 6, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_ATPG, "jtagm0_ATPG", 12, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_ATPG, "jtagm1_ATPG", 12, > + JHB100_SYS2CLK_PLL1),
The ATPG portion of the clock name is uppercase. Can this be lowercase for consistency? Brian -- Brian Masney <[email protected]>
