> Suppose there's I/O to the physical page P asynchronously, and the
> page is placed in the swap cache. It remains cache entry, say,
> indexed kernel virtual address K. Then, process maps P at U. U and K
> (may) indexes differently. The process will get the data from memory
> (not the one in the cashe), if it's not flushed.
Ok we need to handle that case a bit more intelligently so those flushes dont
get into other ports code paths.
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