The dw_dmac was originally developed for avr32 to be used with the Synopsys
DesignWare AHB DMA controller. After 2.6.38, access to the device's i/o
memory was done with the little-endian readl/writel functions
(https://patchwork.kernel.org/patch/608211)
This didn't work on the avr32 platform, because it needs native-endian
(i.e. big-endian) accessors.
This patch makes the endianness configurable using 'DW_DMAC_BIG_ENDIAN_IO',
which will default be true for AVR32
Signed-off-by: Hein Tibosch <hein_tibo...@yahoo.es>
Acked-by: Viresh Kumar <viresh.ku...@linaro.org>
Acked-by: Arnd Bergmann <arnd.bergm...@linaro.org>
Reviewed-by: Hans-Christian Egtvedt <egtv...@samfundet.no>
---
drivers/dma/Kconfig | 11 +++++++++++
drivers/dma/dw_dmac_regs.h | 14 ++++++++++++++
2 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index aadeb5b..a9f6781 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -89,6 +89,17 @@ config DW_DMAC
Support the Synopsys DesignWare AHB DMA controller. This
can be integrated in chips such as the Atmel AT32ap7000.
+config DW_DMAC_BIG_ENDIAN_IO
+ bool "Use big endian I/O register access"
+ default y if AVR32
+ depends on DW_DMAC
+ help
+ Say yes here to use big endian I/O access when reading and writing
+ to the DMA controller registers. This is needed on some platforms,
+ like the Atmel AVR32 architecture.
+
+ If unsure, use the default setting.
+
config AT_HDMAC
tristate "Atmel AHB DMA support"
depends on ARCH_AT91
diff --git a/drivers/dma/dw_dmac_regs.h b/drivers/dma/dw_dmac_regs.h
index f298f69..9758651 100644
--- a/drivers/dma/dw_dmac_regs.h
+++ b/drivers/dma/dw_dmac_regs.h
@@ -175,10 +175,17 @@ __dwc_regs(struct dw_dma_chan *dwc)
return dwc->ch_regs;
}
+#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
+#define channel_readl(dwc, name) \
+ ioread32be(&(__dwc_regs(dwc)->name))
+#define channel_writel(dwc, name, val) \
+ iowrite32be((val), &(__dwc_regs(dwc)->name))
+#else
#define channel_readl(dwc, name) \
readl(&(__dwc_regs(dwc)->name))
#define channel_writel(dwc, name, val) \
writel((val), &(__dwc_regs(dwc)->name))
+#endif
static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
{
@@ -201,10 +208,17 @@ static inline struct dw_dma_regs __iomem
*__dw_regs(struct dw_dma *dw)
return dw->regs;
}
+#ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
+#define dma_readl(dwc, name) \
+ ioread32be(&(__dw_regs(dw)->name))
+#define dma_writel(dwc, name, val) \
+ iowrite32be((val), &(__dw_regs(dw)->name))
+#else
#define dma_readl(dw, name) \
readl(&(__dw_regs(dw)->name))
#define dma_writel(dw, name, val) \
writel((val), &(__dw_regs(dw)->name))
+#endif
#define channel_set_bit(dw, reg, mask) \
dma_writel(dw, reg, ((mask) << 8) | (mask))
--
1.7.8.0
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