On 3 September 2012 14:19, Andy Shevchenko <andy.shevche...@gmail.com> wrote: > On Mon, Sep 3, 2012 at 11:30 AM, Viresh Kumar <viresh.ku...@linaro.org> wrote: >> Which register are you talking about? This configuration is outside of DMAC >> controller and i am not sure if dw DMAC controller can do 128 or 256 >> bit transfers. > SRC_WIDTH & DST_WIDTH in CTLx. The field are 3 bit long. Acceptable > values from 0 to 5. > 2 corresponds to 32 bit transfers.
The field is 3 bit long but only allowable values are 0,1,2 & 3... This is what i can check in my copy of dw_dmac manual. 4 and 5 aren't valid values. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
