3.4-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Simon Horman <[email protected]>

commit 7253b85cc62d6ff84143d96fe6cd54f73736f4d7 upstream.

arm: Add ARM ERRATA 775420 workaround

Workaround for the 775420 Cortex-A9 (r2p2, r2p6,r2p8,r2p10,r3p0) erratum.
In case a date cache maintenance operation aborts with MMU exception, it
might cause the processor to deadlock. This workaround puts DSB before
executing ISB if an abort may occur on cache maintenance.

Based on work by Kouei Abe and feedback from Catalin Marinas.

Signed-off-by: Kouei Abe <[email protected]>
[ [email protected]: Changed to implementation
  suggested by [email protected] ]
Acked-by: Catalin Marinas <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

---
 arch/arm/Kconfig       |   10 ++++++++++
 arch/arm/mm/cache-v7.S |    3 +++
 2 files changed, 13 insertions(+)

--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1405,6 +1405,16 @@ config PL310_ERRATA_769419
          on systems with an outer cache, the store buffer is drained
          explicitly.
 
+config ARM_ERRATA_775420
+       bool "ARM errata: A data cache maintenance operation which aborts, 
might lead to deadlock"
+       depends on CPU_V7
+       help
+        This option enables the workaround for the 775420 Cortex-A9 (r2p2,
+        r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+        operation aborts with MMU exception, it might cause the processor
+        to deadlock. This workaround puts DSB before executing ISB if
+        an abort may occur on cache maintenance.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
  * isn't mapped, just try the next page.
  */
 9001:
+#ifdef CONFIG_ARM_ERRATA_775420
+       dsb
+#endif
        mov     r12, r12, lsr #12
        mov     r12, r12, lsl #12
        add     r12, r12, #4096


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