On 10/28/2012 03:26 PM, Linus Walleij wrote:
On Thu, Oct 25, 2012 at 6:11 PM, Murali Karicheri <[email protected]> wrote:
pll dividers are present in the pll controller of DaVinci and Other
SoCs that re-uses the same hardware IP. This has a enable bit for
bypass the divider or enable the driver. This is a sub class of the
clk-divider clock checks the enable bit to calculare the rate and
invoke the recalculate() function of the clk-divider if enabled.
Signed-off-by: Murali Karicheri <[email protected]>
Looking good,
Acked-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
Linus,
Thanks. I will add your Acked-by in the next version.
Murali
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