From: Rik van Riel <[email protected]> Intel has an architectural guarantee that the TLB entry causing a page fault gets invalidated automatically. This means we should be able to drop the local TLB invalidation.
Because of the way other areas of the page fault code work, chances are good that all x86 CPUs do this. However, if someone somewhere has an x86 CPU that does not invalidate the TLB entry causing a page fault, this one-liner should be easy to revert - or a CPU model specific quirk could be added to retain this optimization on most CPUs. Signed-off-by: Rik van Riel <[email protected]> Acked-by: Linus Torvalds <[email protected]> Acked-by: Peter Zijlstra <[email protected]> Cc: Andrew Morton <[email protected]> Cc: Michel Lespinasse <[email protected]> Cc: Andrea Arcangeli <[email protected]> Cc: Rik van Riel <[email protected]> Cc: Mel Gorman <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Hugh Dickins <[email protected]> [ Applied changelog massage and moved this last in the series, to create bisection distance. ] Signed-off-by: Ingo Molnar <[email protected]> --- arch/x86/mm/pgtable.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index be3bb46..7353de3 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -317,7 +317,6 @@ int ptep_set_access_flags(struct vm_area_struct *vma, if (changed && dirty) { *ptep = entry; pte_update_defer(vma->vm_mm, address, ptep); - __flush_tlb_one(address); } return changed; -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
