hi,
I was looking at the offcore stuff and it looks like we might
be missing some constraints for offcore response events on
Sandy/IvyBridge.
The table 18.8.5 (Off-core Response Performance Monitoring)
in Intel SDM states PMC0 for 0xb7 and PMC3 for 0xbb, but
there's no other explanation or related description.
I can't say/ack if the counters looks bad or right with or
without the patch so far.. so just curious ;-)
thanks,
jirka
---
The Intel SDM (18.8.5 Off-core Response Performance Monitoring)
states the off-core events MSR_OFFCORE_RSP_0/MSR_OFFCORE_RSP_03
to be defined only for PMC0/PMC3 respectively.
Adding related constraints.
Signed-off-by: Jiri Olsa <jo...@redhat.com>
Cc: Arnaldo Carvalho de Melo <a...@redhat.com>
Cc: Namhyung Kim <namhy...@kernel.org>
Cc: Corey Ashford <cjash...@linux.vnet.ibm.com>
Cc: Frederic Weisbecker <fweis...@gmail.com>
Cc: Ingo Molnar <mi...@elte.hu>
Cc: Namhyung Kim <namhy...@kernel.org>
Cc: Paul Mackerras <pau...@samba.org>
Cc: Peter Zijlstra <a.p.zijls...@chello.nl>
Cc: Stephane Eranian <eran...@google.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
b/arch/x86/kernel/cpu/perf_event_intel.c
index 5dc54fc..d1f240f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -105,6 +105,8 @@ static struct event_constraint
intel_snb_event_constraints[] __read_mostly =
INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
+ INTEL_EVENT_CONSTRAINT(0xb7, 0x1), /* MSR_OFFCORE_RSP_0 - PMC0 only*/
+ INTEL_EVENT_CONSTRAINT(0xbb, 0x8), /* MSR_OFFCORE_RSP_1 - PMC3 only*/
EVENT_CONSTRAINT_END
};
--
1.7.11.7
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