Re: [PATCH] clk: tegra: Add missing spinlock for hclk and pclk

[Prashant Gaikwad]

On Thursday 07 February 2013 10:07 PM, Peter De Schrijver wrote:

The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.

Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com>

Reviewed-by: Prashant Gaikwad <pgaik...@nvidia.com>

---
  drivers/clk/tegra/clk-tegra20.c |   11 +++++++----
  drivers/clk/tegra/clk-tegra30.c |   11 +++++++----
  2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5d41569..4612b2e 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -194,6 +194,7 @@ static void __iomem *clk_base;
  static void __iomem *pmc_base;

static DEFINE_SPINLOCK(pll_div_lock);

+static DEFINE_SPINLOCK(sysrate_lock);

#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \

                            _clk_num, _regs, _gate_flags, _clk_id)      \
@@ -768,19 +769,21 @@ static void tegra20_super_clk_init(void)

/* HCLK */

        clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
-                                  clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL);
+                                  clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
+                                  &sysrate_lock);
        clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
                                clk_base + CLK_SYSTEM_RATE, 7,
-                               CLK_GATE_SET_TO_DISABLE, NULL);
+                               CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
        clk_register_clkdev(clk, "hclk", NULL);
        clks[hclk] = clk;

/* PCLK */

        clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
-                                  clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL);
+                                  clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
+                                  &sysrate_lock);
        clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
                                clk_base + CLK_SYSTEM_RATE, 3,
-                               CLK_GATE_SET_TO_DISABLE, NULL);
+                               CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
        clk_register_clkdev(clk, "pclk", NULL);
        clks[pclk] = clk;

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c

index d169ef0..c5415ce 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -275,6 +275,7 @@ static DEFINE_SPINLOCK(clk_out_lock);
  static DEFINE_SPINLOCK(pll_div_lock);
  static DEFINE_SPINLOCK(cml_lock);
  static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(sysrate_lock);

#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \

                            _clk_num, _regs, _gate_flags, _clk_id)      \
@@ -1348,19 +1349,21 @@ static void __init tegra30_super_clk_init(void)

/* HCLK */

        clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
-                                  clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL);
+                                  clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
+                                  &sysrate_lock);
        clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
                                clk_base + SYSTEM_CLK_RATE, 7,
-                               CLK_GATE_SET_TO_DISABLE, NULL);
+                               CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
        clk_register_clkdev(clk, "hclk", NULL);
        clks[hclk] = clk;

/* PCLK */

        clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
-                                  clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL);
+                                  clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
+                                  &sysrate_lock);
        clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
                                clk_base + SYSTEM_CLK_RATE, 3,
-                               CLK_GATE_SET_TO_DISABLE, NULL);
+                               CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
        clk_register_clkdev(clk, "pclk", NULL);
        clks[pclk] = clk;

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