I have found a comment in function physflat_cpu_mask_to_apicid to explain why.
static unsigned int physflat_cpu_mask_to_apicid(const struct cpumask *cpumask)
{
int cpu;
/*
* We're using fixed IRQ delivery, can only return one phys APIC ID.
* May as well be the first.
*/
...
This is mean i can not distribute the interrupts over multiple cores
when the machine have more than 8 cores?
--
Regards,
Lenky
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