Upcoming AMD Family 16h Processors provide 4 new performance counters to count L2 related events. Similar to northbridge counters, these new counters are shared across multiple CPUs that share the same L2 cache. This patchset adds support for these new counters and enforces sharing by leveraging the existing sharing logic used for the northbridge counters.
Jacob Shin (3): perf, amd: Further generalize NB event constraints handling logic perf, x86: Allow for multiple kfree_on_online pointers perf, amd: Enable L2I performance counters on AMD Family 16h arch/x86/include/asm/cpufeature.h | 2 + arch/x86/include/asm/perf_event.h | 4 + arch/x86/include/uapi/asm/msr-index.h | 4 + arch/x86/kernel/cpu/perf_event.c | 7 +- arch/x86/kernel/cpu/perf_event.h | 11 +- arch/x86/kernel/cpu/perf_event_amd.c | 227 +++++++++++++++++++++++++------- arch/x86/kernel/cpu/perf_event_intel.c | 2 +- 7 files changed, 199 insertions(+), 58 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
