At 3:41 pm +0100 5/5/2001, Alan Cox wrote:
>> My wild guess is that with the "faster" code, the K7 is avoiding loading
>> cache lines just to write them out again, and is just writing tons of data.
>> The PPC G4 - and perhaps even the G3 - performs a similar trick
>> automatically, without special assembly...
>
>X86 has done that since the K5 era.
>
>No the main thing that the mmx copier does is to read and write in 64bit
>wide chunks
Just for the record, this can be done on any PPC, by using the FPU
registers (which are much faster than x86 FPU). AltiVec can do 128-bit
wide transfers.
>and then more importantly to prefetch pending data.
That's a tougher one. AltiVec (in the G4) can do this, but I suspect it
can be emulated using the pipeline on earlier PowerPCs, by queueing up a
line of FPU load instructions and then a queue of FPU saves. However, the
601 and 603 don't have a superscalar FPU, though I wonder if that would
actually affect a simple load/store operation.
This is rapidly getting offtopic, though...
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