Stephen Warren <swar...@wwwdotorg.org> :
> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for
> the BCM2835 chip), I see:
>
> =====
> The UART provides:
> * Separate 16x8 transmit and 16x12 receive FIFO memory.
> ...
> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
> (PL011) Revision: r1p5 Technical Reference Manual.
> =====
>
> That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO.
> Perhaps this is a configurable property of the IP block, not something
that
> all r1p5 have?
All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011
TRM:
r1p4-r1p5 Contains the following differences in functionality:
* The receive and transmit FIFOs are increased to a depth of
32.
* The Revision field in the UARTPeriphID2 Register on page
3-24
bits [7:4] now reads back as 0x3.
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