On Fri, May 24, 2013 at 07:11:04AM +0000, Yang, Wenyou wrote: > The story is: for sama5d3x with Cortex-A5 core, if not so, when copying > code snippet to the internal SRAM, then jump to run this code, but fail > to run.
And that is where your mistake is - you forgot that you're working with a CPU with harvard caches which will require some cache maintanence between copying the code and executing it. You want to look at flush_icache_range() rather than making this memory strongly ordered. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
