Anshuman Khandual [khand...@linux.vnet.ibm.com] wrote: | > The former approach seems less confusing and this patch uses that approach. | > | | Yeah, the former approach is simpler and makes sense.
Ok. Seems to make sense at least on Power. <snip> | > + * We use the table, dcache_src_map, to map this value 1 to PERF_MEM_LVL_L3, | > + * the arch-neutral representation of the L3 cache. | > + * | > + * Similarly, in case of marked data TLB miss, bits 14..17 of the MMCRA | > + * indicate the load source of a marked DTLB entry. dtlb_src_map[] gives | > + * the mapping to the arch-neutral values of the TLB source. | | | Where did you define dtlb_src_map[] ? Ah, the comment belongs in another patch that I am working on. That patch maps the PERF_MEM_TLB* flags to Power7. Thanks for the comments. Sukadev -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
