Exynos5440 has two PCIe controllers which can be used as root complex
for PCIe interface.
Signed-off-by: Jingoo Han <jg1....@samsung.com>
---
Tested on Exynos5440.
Changes since v3:
- Removed 'bus-range' property from DT
- Added 'interrupt-map-mask', 'interrupt-map' properties to DT
- Fixed the start address of MEM space in DT
- Increased the size of I/O space to 64kB in DT
- Added 'clocks', 'clock-names' properties to DT
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 8 ++++++
arch/arm/boot/dts/exynos5440.dtsi | 38 +++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..efe7d39 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -30,4 +30,12 @@
clock-frequency = <50000000>;
};
};
+
+ pcie0@40000000 {
+ reset-gpio = <5>;
+ };
+
+ pcie1@60000000 {
+ reset-gpio = <22>;
+ };
};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..2c15f9d 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -216,4 +216,42 @@
clock-names = "rtc";
status = "disabled";
};
+
+ pcie0@0x290000 {
+ compatible = "samsung,exynos5440-pcie";
+ reg = <0x290000 0x1000
+ 0x270000 0x1000
+ 0x271000 0x40>;
+ interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+ clocks = <&clock 28>, <&clock 27>;
+ clock-names = "pcie", "pcie_bus";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00200000 /*
configuration space */
+ 0x81000000 0 0 0x40200000 0 0x00010000 /*
downstream I/O */
+ 0x82000000 0 0x40210000 0x40210000 0 0x10000000>; /*
non-prefetchable memory */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 53>;
+ };
+
+ pcie1@2a0000 {
+ compatible = "samsung,exynos5440-pcie";
+ reg = <0x2a0000 0x1000
+ 0x272000 0x1000
+ 0x271040 0x40>;
+ interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+ clocks = <&clock 29>, <&clock 27>;
+ clock-names = "pcie", "pcie_bus";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00200000 /*
configuration space */
+ 0x81000000 0 0 0x60200000 0 0x00010000 /*
downstream I/O */
+ 0x82000000 0 0x60210000 0x60210000 0 0x10000000>; /*
non-prefetchable memory */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0x0 0 &gic 56>;
+ };
};
--
1.7.10.4
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