This patch adds support for sampling the physical data address
of Loads/Stores captured by PEBS Load Latency/Precise Store
facility.
Signed-off-by: Stephane Eranian <eran...@google.com>
---
arch/x86/kernel/cpu/perf_event_intel_ds.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c
b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 06d02fa..e32a5ab 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -3,6 +3,7 @@
#include <linux/slab.h>
#include <asm/perf_event.h>
+#include <asm/uaccess.h>
#include <asm/insn.h>
#include "perf_event.h"
@@ -835,10 +836,14 @@ static void __intel_pmu_pebs_event(struct perf_event
*event,
else
regs.flags &= ~PERF_EFLAGS_EXACT;
- if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
+ if ((sample_type & PERF_SAMPLE_ADDR) &&
x86_pmu.intel_cap.pebs_format >= 1)
data.addr = pebs->dla;
+ if ((fll || fst) && (sample_type & PERF_SAMPLE_PHYS_ADDR) &&
+ x86_pmu.intel_cap.pebs_format >= 1)
+ data.phys_addr = uvirt_to_phys_nmi((void *)(pebs->dla));
+
if (has_branch_stack(event))
data.br_stack = &cpuc->lbr_stack;
--
1.8.1.2
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