Hi Jens,
   Sorry to disturb you, do you have any comments for this patch?

Thanks!
Yijing.

On 2013/6/18 16:19, Yijing Wang wrote:
> Use pci core pm interface to simplify code.
> 
> Signed-off-by: Yijing Wang <wangyij...@huawei.com>
> Cc: Mike Miller <mike.mil...@hp.com>
> Cc: iss_storage...@hp.com
> Cc: linux-kernel@vger.kernel.org
> ---
>  drivers/block/cciss.c |   16 +++-------------
>  1 files changed, 3 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
> index 62b6c2c..18da685 100644
> --- a/drivers/block/cciss.c
> +++ b/drivers/block/cciss.c
> @@ -4528,9 +4528,6 @@ static int cciss_message(struct pci_dev *pdev, unsigned 
> char opcode,
>  static int cciss_controller_hard_reset(struct pci_dev *pdev,
>       void * __iomem vaddr, u32 use_doorbell)
>  {
> -     u16 pmcsr;
> -     int pos;
> -
>       if (use_doorbell) {
>               /* For everything after the P600, the PCI power state method
>                * of resetting the controller doesn't work, so we have this
> @@ -4548,8 +4545,7 @@ static int cciss_controller_hard_reset(struct pci_dev 
> *pdev,
>                * this causes a secondary PCI reset which will reset the
>                * controller." */
>  
> -             pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
> -             if (pos == 0) {
> +             if (!pdev->pm_cap) {
>                       dev_err(&pdev->dev,
>                               "cciss_controller_hard_reset: "
>                               "PCI PM not supported\n");
> @@ -4557,18 +4553,12 @@ static int cciss_controller_hard_reset(struct pci_dev 
> *pdev,
>               }
>               dev_info(&pdev->dev, "using PCI PM to reset controller\n");
>               /* enter the D3hot power management state */
> -             pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
> -             pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
> -             pmcsr |= PCI_D3hot;
> -             pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
> +             pci_set_power_state(pdev, PCI_D3hot);
>  
>               msleep(500);
>  
>               /* enter the D0 power management state */
> -             pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
> -             pmcsr |= PCI_D0;
> -             pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
> -
> +             pci_set_power_state(pdev, PCI_D0);
>               /*
>                * The P600 requires a small delay when changing states.
>                * Otherwise we may think the board did not reset and we bail.
> 


-- 
Thanks!
Yijing

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