Hi, On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote: > Exynos PCIe IP consists of Synopsys specific part and Exynos > specific part. Only core block is a Synopsys designware part; > other parts are Exynos specific. > Also, the Synopsys designware part can be shared with other > platforms; thus, it can be split two parts such as Synopsys > designware part and Exynos specific part. > > Signed-off-by: Jingoo Han <[email protected]> > Cc: Pratyush Anand <[email protected]> > Cc: Mohit KUMAR <[email protected]> > --- . . <snip> . . > + > +/* Exynos PCIe driver does not allow module unload */
Just curious, why is this restriction? Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
