On 29/07/13 13:29, Sebastian Hesselbarth wrote: > This adds a node for the Marvell Sheeva PJ4A CPU found on Dove SoCs. > While at it, also move the l2-cache node out of internal registers and > consistently name different nodes. > > Signed-off-by: Sebastian Hesselbarth <[email protected]> > --- > Cc: Russell King <[email protected]> > Cc: Jason Cooper <[email protected]> > Cc: Andrew Lunn <[email protected]> > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > --- > arch/arm/boot/dts/dove.dtsi | 52 > ++++++++++++++++++++++++++----------------- > 1 file changed, 32 insertions(+), 20 deletions(-) > > diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi > index 8d5be1e8..09d9710 100644 > --- a/arch/arm/boot/dts/dove.dtsi > +++ b/arch/arm/boot/dts/dove.dtsi > @@ -10,6 +10,23 @@ > gpio2 = &gpio2; > }; > > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "marvell,pj4a", "marvell,sheeva-v7"; > + device_type = "cpu"; > + next-level-cache = <&l2>; > + reg = <0>; > + }; > + }; > + > + l2: l2-cache { > + compatible = "marvell,tauros2-cache"; > + marvell,tauros2-cache-features = <0>; > + }; Hi Sebastian,
This is not entirely related to the patch but thought of checking with you. I was trying to get info on L2 cache controller on Marvell SoCs, mainly structure or way/set size. Is that something we can get dynamically ? Some specification I referred said its integrated and some said its separate(not unified). Basically I need information around various L2 cache implementations(Tauros2/Feroceon) from Marvell. Any pointers or contacts to get this information will be helpful. Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
