(2013/08/07 14:03), H. Peter Anvin wrote: > On 08/06/2013 09:51 PM, Masami Hiramatsu wrote: >> >> Thanks, Andi also asked me to support them ;) >> As far as I can see, that requires more work to support >> EVEX decoding. And perhaps, I have to classify new instructions >> and operands and introduce new abbreviations/superscripts for >> them, because there is no opcode map in the above document. >> >> Would you intel guys have any idea about new opcode map? >> > > What is it you need, specifically?
A new opcode map about AVX-512, which introduces ZMM registers which has 512-bit width. Perhaps, we need to introduce new code of operand type for that new large registers, I guess it is Octa-Quadword(oq)? :) And also, MASK instructions may require new addressing method codes for opmask registers. Of course I can make new one for those and update after official opcode map is released, as I did on AVX instructions. Thank you, -- Masami HIRAMATSU IT Management Research Dept. Linux Technology Center Hitachi, Ltd., Yokohama Research Laboratory E-mail: masami.hiramatsu...@hitachi.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/