On Mon, Aug 19, 2013 at 04:24:56PM +0200, Stephane Eranian wrote: > On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng <[email protected]> wrote: > > From: "Yan, Zheng" <[email protected]> > > > > Silvermont (22nm Atom) has two offcore response configuration MSRs, > > unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7. > > To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to > > define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event code > > for OFFCORE_RSP_N by x86_pmu.extra_regs[N].event. > > > > Signed-off-by: Yan, Zheng <[email protected]> > > Works for me on IVB and NHM. > > Reviewed-by: Stephane Eranian <[email protected]>
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