On Mon, Aug 19, 2013 at 03:07:53PM +0300, Mika Westerberg wrote: > The DesignWare I2C controller has high count (HCNT) and low count (LCNT) > registers for each of the I2C speed modes (standard and fast). These > registers are programmed based on the input clock speed in the driver. > > The current code calculates these values based on the input clock speed and > tries hard to meet the I2C bus timing requirements. This could result > non-optimal values with regarding to the bus speed. For example on Intel > BayTrail we get bus speed of 315.41kHz which is ~20% slower than we would > expect (400kHz) in fast mode (even though the timing requirements are met). > > This patch makes it possible for the platform code to pass more optimal > HCNT/LCNT values to the core driver if they are known beforehand. If these > are not set we use the calculated and more conservative values. > > Signed-off-by: Mika Westerberg <[email protected]>
Applied to for-next, thanks!
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