This patch converts the Tegra114 PMC clock registration to be table driven
like the periph clocks.
Signed-off-by: Peter De Schrijver <pdeschrij...@nvidia.com>
---
Fix comment :)
---
drivers/clk/tegra/clk-tegra114.c | 58 +++++++++++++++-----------------------
1 files changed, 23 insertions(+), 35 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 0379a19..44ba713 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1583,45 +1583,33 @@ static void __init tegra114_audio_clk_init(void __iomem
*clk_base)
}
}
+static struct pmc_clk_init_data tegra_pmc_clk_init_data[] = {
+ TEGRA_INIT_PMC_CLK("clk_out_1", "extern1", clk_out1_parents, 6, 2,
TEGRA114_CLK_CLK_OUT_1),
+ TEGRA_INIT_PMC_CLK("clk_out_2", "extern2", clk_out2_parents, 14, 10,
TEGRA114_CLK_CLK_OUT_2),
+ TEGRA_INIT_PMC_CLK("clk_out_3", "extern3", clk_out3_parents, 22, 18,
TEGRA114_CLK_CLK_OUT_3),
+};
+
static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
{
struct clk *clk;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tegra_pmc_clk_init_data); i++) {
+ struct pmc_clk_init_data *data;
- /* clk_out_1 */
- clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
- ARRAY_SIZE(clk_out1_parents), 0,
- pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
- &clk_out_lock);
- clks[TEGRA114_CLK_CLK_OUT_1_MUX] = clk;
- clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
- pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
- &clk_out_lock);
- clk_register_clkdev(clk, "extern1", "clk_out_1");
- clks[TEGRA114_CLK_CLK_OUT_1] = clk;
-
- /* clk_out_2 */
- clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
- ARRAY_SIZE(clk_out2_parents), 0,
- pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
- &clk_out_lock);
- clks[TEGRA114_CLK_CLK_OUT_2_MUX] = clk;
- clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
- pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
- &clk_out_lock);
- clk_register_clkdev(clk, "extern2", "clk_out_2");
- clks[TEGRA114_CLK_CLK_OUT_2] = clk;
-
- /* clk_out_3 */
- clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
- ARRAY_SIZE(clk_out3_parents), 0,
- pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
- &clk_out_lock);
- clks[TEGRA114_CLK_CLK_OUT_3_MUX] = clk;
- clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
- pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
- &clk_out_lock);
- clk_register_clkdev(clk, "extern3", "clk_out_3");
- clks[TEGRA114_CLK_CLK_OUT_3] = clk;
+ data = &tegra_pmc_clk_init_data[i];
+
+ clk = clk_register_mux(NULL, data->mux_name, data->parents,
+ data->num_parents, 0,
+ pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
+ 3, 0, &clk_out_lock);
+ clks[data->mux_id] = clk;
+ clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
+ 0, pmc_base + PMC_CLK_OUT_CNTRL,
+ data->gate_shift, 0, &clk_out_lock);
+ clks[data->gate_id] = clk;
+ clk_register_clkdev(clk, data->dev_name, data->gate_name);
+ }
/* blink */
/* clear the blink timer register to directly output clk_32k */
--
1.7.7.rc0.72.g4b5ea.dirty
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