On 09/19/2013 01:17 PM, Pavel Machek wrote: > Hi! > >>> This code also creates a set of files under /sys for each separate fpga. >>> I.e. checking status by looking at /sys/class/fpga/fpag0/status. It >>> would be pretty small changes to control reseting the fpga by adding a >>> 'reset' file there also (added first to the framework, and an interface >>> into the low level fpga manager driver). >> >> Status is just there and for my zynq devcfg driver I do export some status >> bits. >> >> root@petalinux:~# cat /sys/class/fpga/fpga0/status >> partial_bitstream_status: 0 >> prog_done_status: 1 >> dbg_lock_status: 0 >> seu_lock_status: 0 >> aes_en_lock_status: 0 >> aes_status: 0 >> seu_status: 0 >> spniden_status: 1 >> spiden_status: 1 >> niden_status: 1 >> dbgen_status: 1 >> dap_en_status: 7 > > This is single file? If so, it needs to be changed. Greg is rather > clear about that.
Don't you have a link to these rules? I have seen any paragraph from Greg about it but I forget where was it. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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