On Mon, 2013-09-23 at 13:59 -0400, Chris Metcalf wrote: > We just came up against this on tilegx with a customer bug report in a > PREEMPT environment. On tile, %tp is a GPR that points to the percpu area. > The following seems to be the right abstraction -- though I'd also argue > that letting barrier() clobber not just memory, but %tp, might be a better > solution, but it's not clear what the best way is to do per-architecture > overrides of per-compiler definitions like barrier(). See also the ARM v7 > code, which has to do something similar, though their percpu pointer is > not a GPR, which changes the tradeoffs somewhat.
Hrm, if I read correctly what you did is that you read "tp" into another register *and* also mark that action as clobbering the top int on the stack ? I don't quite get what the stack clobber brings you here and how it works around the fact that gcc might still cache that copy of tp into another register accross preempt_enable/disable... It's hard to tell with gcc ... the best I've had so far as an option was something that would mark my per-cpu register (r13) *itself* as clobbered... Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
