Hi, I'm seeing the following issue on omap3 with dpll4_m4 clock. dpll4_m4's parent is a PLL set to 864000000 and dpll4_m4 is a divider, handled by clk-divider.c.
Now, if I call clk_round_rate(dpll4_m4, 143999999), I get 123428571 which is correct. However, if I call clk_round_rate(dpll4_m4, 123428571), I would presume to get the same answer, 123428571, as that was already "verified" by the previous clk_round_rate() call. However, I get 108000000. So, if I have the following code: rate = clk_round_rate(dpll4_m4, 143999999); /* rate is 123428571 */ clk_set_rate(dpll4_m4, rate); the resulting rate is 108000000. Tomi
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