On Sun, Oct 20, 2013 at 08:26:49PM -0700, Benson Leung wrote:
> From: Duncan Laurie <dlau...@chromium.org>
>
> Add the necessary PCI Device IDs to use the Haswell ULT
> I2C controller in PCI mode.
>
> Set the bus numbers to -1 so it will use dynamic assignment
> rather than hardcoded.
>
> Signed-off-by: Duncan Laurie <dlau...@chromium.org>
> Signed-off-by: Benson Leung <ble...@chromium.org>
Looks good to me, except one thing...
> ---
> drivers/i2c/busses/i2c-designware-pcidrv.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c
> b/drivers/i2c/busses/i2c-designware-pcidrv.c
> index f6ed06c..e4cbbdf 100644
> --- a/drivers/i2c/busses/i2c-designware-pcidrv.c
> +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
> @@ -54,6 +54,9 @@ enum dw_pci_ctl_id_t {
> medfield_3,
> medfield_4,
> medfield_5,
> +
> + haswell_0,
> + haswell_1,
> };
>
> struct dw_pci_controller {
> @@ -132,6 +135,20 @@ static struct dw_pci_controller dw_pci_controllers[] =
> {
> .rx_fifo_depth = 32,
> .clk_khz = 25000,
> },
> + [haswell_0] = {
> + .bus_num = -1,
> + .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
> + .tx_fifo_depth = 32,
> + .rx_fifo_depth = 32,
> + .clk_khz = 25000,
The input clock for I2C in Haswell is 100MHz, not 25MHz.
> + },
> + [haswell_1] = {
> + .bus_num = -1,
> + .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
> + .tx_fifo_depth = 32,
> + .rx_fifo_depth = 32,
> + .clk_khz = 25000,
Ditto.
> + },
> };
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