On 10/22/2013 06:05 PM, Lee Jones wrote: >> I added reg_se_cache to cache the content of REG_SE once and >> synchronize it among TSC & ADC access. REG_SE is set to 0 by the HW >> after "work" has been done. So you need to know the old value or TSC may >> disable ADC and the other way around. > > Yep, it's initialised as '0'. > > 12.5.1.15 STEPENABLE Register (offset = 54h) [reset = 0h]
Ehm yes but!. After init it is set to 0, correct. The value was never read from the HW. It was always set via am335x_tsc_se_set() to "cache | argument" and written to HW from both sides (TSC, ADC). This initialization is done at ->probe() time in both drivers. The value remains (remained) constant over the whole time so both drivers only called am335x_tsc_se_update() to set the value (the enabled steps of both sides) back to the register (because after the conversation the value was 0 according to my memory) and since 32bit reads are atomic I didn't use a lock here. Sebastian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
