On Tue, Nov 12, 2013 at 06:46:20PM +0000, Luck, Tony wrote: > > So the point we're having a discussion on is if any architecture has > > visible speculative STORES and if there's an architecture that doesn't > > have control dependencies. > > > > On the visible speculative STORES; can, if in the above example we have > > regular loads/stores: > > > > LOAD r1, x LOAD r2, y > > IF (r1) IF (r2) > > STORE y, 1 STORE x, 1 > > > > we observe: r1==1 && r2==1 > > > > In order for that to be true; we must be able to observe the stores > > before the loads are complete -- and therefore before the branches are a > > certainty. > > Even without the ".acq" and ".rel" this code is still safe. > > Quoting ia64 SDM vol 1, Section 4.4.7 Memory Access Ordering" > "In addition, memory writes and flushes must observe control dependencies" > > which I take to mean that the STORE can't be visible until we are certain of > the outcome of the conditional.
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