On Wed, Nov 13, 2013 at 04:13:57PM +0000, Arjan van de Ven wrote: > On 11/12/2013 3:14 PM, Catalin Marinas wrote: > > On 12 Nov 2013, at 16:48, Arjan van de Ven <ar...@linux.intel.com> wrote: > >> On 11/11/2013 10:18 AM, Catalin Marinas wrote: > >>> The ordering is based on the actual C-state, so a simple way is to wake > >>> up the CPU in the shallowest C-state. With asymmetric configurations > >>> (big.LITTLE) we have different costs for the same C-state, so this would > >>> come in handy. > >> > >> btw I was considering something else; in practice CPUs will be in the > >> deepest state.. > >> ... at which point I was going to go with some other metrics of what is > >> best from a platform level > > > > I agree, other metrics are needed. The problem is that we currently > > only have (relatively, guessed from the target residency) the cost of > > transition from a C-state to a P-state (for the latter, not sure which). > > But we don’t know what the power (saving) on that C-state is nor the one > > at a P-state (and vendors reluctant to provide such information). So the > > best the scheduler can do is optimise the wake-up cost and blindly assume > > that deeper C-state on a CPU is more efficient than lower P-states on two > > other CPUs (or the other way around). > > for picking the cpu to wake on there are also low level physical kind of > things > we'd want to take into account on the intel side.
Are these static and could they be hidden behind some cost number in a topology description? If they are dynamic, we would need arch or driver hooks to give some cost or priority number that the scheduler can use. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
